The present invention relates generally to producing a reference frequency signal input for a phase locked loop (PLL), and more particularly to methods and apparatus for producing a reference frequency signal for a PLL with use of a reference frequency doubler.
A conventional phase locked loop (PLL) typically includes a frequency phase detector which receives a reference signal, a filter, a voltage-controlled oscillator (VCO), and a divider circuit. If the reference signal received by the frequency phase detector has a relatively low frequency, a large feedback divider ratio is required by the PLL. A large feedback divider ratio requires that the divider circuit have a relatively large number of dividers, which undesirably introduces phase xe2x80x9cjitterxe2x80x9d into the signals. The large feedback divider ratio also means that the loop gain of the PLL will be lower for a given supply voltage, which makes the gain distribution for noise less ideal and also increases jitter.
According to the present invention, circuitry for a phase locked loop (PLL) includes a reference signal input for providing a first reference signal having a first frequency. The circuitry further includes a frequency doubler that doubles the first frequency of the first reference signal, to produce a second reference signal having a second frequency that is approximately twice the first frequency. The second reference signal is received by a frequency phase detector of the PLL, which further includes a filter and voltage controlled oscillator that receives an output of the frequency phase detector, and a divider that receives the output of the filter and VCO. The output of the divider is looped back to the frequency phase detector for comparison with the second reference signal.
The increased (doubled) reference frequency allows the PLL to have a smaller feedback divider ratio and therefore fewer dividers; fewer dividers result in less circuitry in the PLL feedback path which reduces jitter. A reduced divider ratio also allows a higher loop gain for a given supply voltage, which produces a more ideal gain distribution for noise and reduces jitter as well. The frequency doubler is provided with selection control for programming multiple frequencies.